Volodymyr kratyuk thesis


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From this intermediate node the charge pump clock output signal is coupled via a capacitor e. The modified capacitive coupling circuit for the FET provides an example of a modified circuit that differs in some regard, but functions substantially equivalently, to another. Any circuit illustrated or described herein may be replaced as needed by such a modified circuit, if substantially the same function is performed.

Extended voltage capacity circuits, such as series or cascode-coupled transistors or the series capacitors described above, and increased current capacity circuits, such as parallel combinations of transistors, are examples of such equivalent circuits that may be employed, in place of any illustrated circuit, to satisfy particular design goals. In the exemplary circuit, N-channel switches such as FETs and are switched on concurrently while P-channel switches such as FETs and are off, and the converse is also true. The gate threshold voltage of N-channel switches is positive e.

Single-phase clock drive of a charge pump may be effected using different types of switches that have correspondingly different control voltage thresholds. However, bias voltages may need to be adjusted accordingly to avoid simultaneous conduction of devices, such as FETs and , that are disposed in series across a supply. The circuits and devices of FIG. Each capacitive gate drive circuit shown in FIG. In the exemplary circuit of FIG. Such voltage division may reduce the magnitude of the control node voltage Vgs , and hence may reduce conductivity of the switches when they are nominally enabled.

Charge pumps are extremely versatile, and aspects of the charge pump method and apparatus herein may be employed in virtually any charge pump configuration. Some alternative techniques are set forth below, each of which may be implemented using aspects of the method and apparatus described herein. A transfer capacitor charges via the clock source and via a passive switch when CLK is at a maximum value. When CLK is at a minimum value, the transfer capacitor discharges via the clock sink and a passive switch Passive switch may similarly be a diode-connected N-channel enhancement FET, or may be a discrete diode with anode to output capacitor , cathode to transfer capacitor However, there is some loss of efficiency and voltage output due to the non-zero forward conduction voltage of the devices and Thus, if CLK is 3V p-p e.

Passive switches similar to devices or may be substituted in place of one or more active switches in many designs described herein, simplifying design but typically reducing output voltage. For example, in FIG. Passive switches are controlled by a charge pump clock output, but not via a control node.

Rather, connections to primary conduction nodes of such switches are driven, through circuit operation controlled by a charge pump clock output, to voltage levels at which the devices passively switch on or off.

A switching-based phase noise model for CMOS ring oscillators based on multiple thresholds crossing

Each is driven by a clock CLK With the bias resistor connected to the source of the FET , it is preferable that the FET has a small negative threshold voltage e. In this circumstance, it is preferred that the threshold voltage for the FET has a small positive value e.

Session 3: The Ukraine Conflict (Q&A)

P-switches and n-switches may have different thresholds while operating from a common clock signal, provided that the bias voltage is set properly to ensure that a p-switch and an n-switch connected in series across a supply are precluded from concurrent conduction. Each switch and may be as illustrated in FIG. The circuit of FIG. Ve may be connected to Vd , and Vf may be connected to ground. A storage capacitor, though not shown, is generally provided somewhere to store and smooth each of the voltages Va , Vc , Vd , Ve , Vg and Vh Vc and Va may be connected to Vf Capacitive storage, not shown, is assumed for each supply and intermediate voltage.

Alternatively, a single phase of a first clock may control the switches connected to the fly capacitor i. If the clocks for charge pump sections and are inverted from one another, then the charge pump sections may be disposed in parallel to create a push-pull charge pump. Such a push-pull charge pump may, for example, provide lower ripple voltage and higher output current capabilities.

Descriptions

Additionally, in circuits otherwise comporting with FIG. The left-side switches of section of FIG. In such a configuration, transfer capacitor charging current and discharging current may be limited not only by a drive signal such as that on capacitor in FIG. Such intermediate voltage may optionally be buffered, if significant current output is desired, by means of buffer amplifier , or may at least be connected to ground via a decoupling capacitor not shown , to produce a projection voltage with respect to common, or ground. The projection voltage may be regulated, for example by means of feedback not shown applied to amplifier P-switches and n-switches may be employed in conjunction with a fly capacitor , as shown.

Vb may be an available voltage source e. Operation of the circuit will establish Va at a voltage approximately equal to that of Vb plus the projection voltage The skilled person will readily see that rearrangement of the circuit will permit generation of arbitrary negative voltages with equal simplicity. Larger voltages may be obtained by stacking charge pump circuits, in a manner as described with respect to FIG. Thus, arbitrary positive or negative voltages may be generated by means of charge pump circuits.

All such charge pump circuits may be controlled by a single phase of a clock. Of course, the switches associated with different fly capacitors may alternatively use different clocks for control. Active switches may also be replaced with passive switches, for example in a manner as described with respect to FIG. Innumerable alternative embodiments of the charge pumps described above are possible.

Any clock generator may be employed. It may be desirable to capacitively couple a charge pump clock to a control node of a transfer capacitor switch, for example in order to simplify control of control-node voltage levels. It may be desirable to utilize a single-phase clock output to control many, or all, of the transfer capacitor active switches within a charge pump, to minimize circuit complexity. Any of these desirable features may be effected independently, or in combination with any of the other desirable features, or in combination with any other feature described herein.

Thus, the skilled person may apply aspects of the method and apparatus described herein to a staggering variety of charge pump configurations. The foregoing description illustrates exemplary implementations, and novel features, of aspects of a charge pump method and apparatus for generating new voltages in circuits. The skilled person will understand that various omissions, substitutions, and changes in the form and details of the methods and apparatus illustrated may be made without departing from the scope of the invention.

Numerous alternative implementations have been described, but it is impractical to list all embodiments explicitly. As such, each practical combination of apparatus and method alternatives that are set forth above or shown in the attached figures, and each practical combination of equivalents of such apparatus and method alternatives, constitutes a distinct alternative embodiment of the subject apparatus or methods. Therefore, the scope of the presented invention should be determined only by reference to the appended claims, and is not to be limited by features illustrated in the foregoing description except insofar as such limitation is recited in an appended claim.

All variations coming within the meaning and range of equivalency of the various claim elements are embraced within the scope of the corresponding claim. Each claim set forth below is intended to encompass any system or method that differs only insubstantially from the literal language of such claim, as long as such system or method is not, in fact, an embodiment of the prior art. To this end, each described element in each claim should be construed as broadly as possible, and moreover should be understood to encompass any equivalent to such element insofar as possible without also encompassing the prior art.

Effective date : Year of fee payment : 4. A charge pump method and apparatus is described having various aspects. Noise injection from a charge pump to other circuits may be reduced by limiting both positive and negative clock transition rates, as well as by limiting drive currents within clock generator driver circuits, and also by increasing a control node AC impedance of certain transfer capacitor coupling switches.

A single-phase clock may be used to control as many as all active switches within a charge pump, and capacitive coupling may simplify biasing and timing for clock signals controlling transfer capacitor coupling switches. Charge Pump Noise As noted above, noise is one of the most common problems associated with charge pumps. Alternative Charge Pump Embodiments Charge pumps are extremely versatile, and aspects of the charge pump method and apparatus herein may be employed in virtually any charge pump configuration.

Conclusion The foregoing description illustrates exemplary implementations, and novel features, of aspects of a charge pump method and apparatus for generating new voltages in circuits. What is claimed is: 1. A capacitive energy transfer converter including: a at least one capacitive charge pump controlled by at least one clock input signal, for providing an output voltage supply based upon a coupled source voltage;.

The capacitive energy transfer converter of claim 1 , wherein the one or more capacitive coupling networks are configured such that the clock signal provides substantial charge to the output voltage of the at least one capacitive charge pump. The capacitive energy transfer converter of claim 1 , wherein the one or more capacitive coupling networks are configured such that the clock signal does not conduct substantial charge to the output voltage of the at least one capacitive charge pump. The capacitive energy transfer converter of claim 1 , wherein the clock circuit is configured as a current starved ring oscillator.

The capacitive energy transfer converter of claim 1 , wherein the current limiter circuitry is configured to limit the source current and sink current to a substantially identical magnitude. The capacitive energy transfer converter of claim 1 , wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter.

The capacitive energy transfer converter of claim 1 , wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit. A capacitive energy transfer converter including: a at least one capacitive charge pump controlled by at least one clock input signal, for providing an output voltage supply based upon a coupled source voltage; and. The capacitive energy transfer converter of claim 8 , further including circuitry configured to reduce voltage change rates of the clock signal during both positive and negative transitions such that the clock signal is substantially sine-like and wherein the capacitive coupling of the clock signal necessitates that the clock signal be substantially sine-like.

The capacitive energy transfer converter of claim 8 , further including circuitry in the clock generating circuit configured to limit currents in the generation of the clock signal. The capacitive energy transfer converter of claim 8 , wherein the clock signal from the clock generating circuit is a single-phase clock signal. The capacitive energy transfer converter of claim 8 , wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter.

The capacitive energy transfer converter of claim 8 , wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit. The capacitive energy transfer converter of claim 14 , wherein the clock generating circuit further includes current limiter circuitry for limiting currents in the generation of the clock signal. The capacitive energy transfer converter of claim 14 , wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter.

The capacitive energy transfer converter of claim 14 , wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit. A capacitive energy transfer converter including: a at least one capacitive charge pump controlled by at least one single-phase clock input signal, for providing an output voltage based upon a coupled source voltage;. The capacitive energy transfer converter of claim 18 , wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter.

The capacitive energy transfer converter of claim 18 , wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit. A capacitive energy transfer converter for generating an output supply within a monolithic integrated circuit by alternately transferring charge from a voltage source to a transfer capacitor and from the transfer capacitor to the output supply, including single-phase charge pump clock circuitry configured to: a couple the transfer capacitor to the output supply during discharge periods via a transfer capacitor discharging switch under control of a single-phase substantially sine-like charge pump clock output that is capacitively coupled to a control node of the transfer capacitor discharging switch and substantially isolated from the transfer capacitor; and.

The capacitive energy transfer converter of claim 21 , wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter. A capacitive energy transfer converter including: a at least one capacitive charge pump controlled by at least one single-phase clock input signal, for providing an output voltage supply based upon a coupled source voltage by alternately charging and discharging an associated transfer capacitor during non-overlapping periods in response to the single-phase clock signal; and.

The capacitive energy transfer converter of claim 23 , wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter. The capacitive energy transfer converter of claim 23 , wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit.

The capacitive energy transfer converter of claim 26 , wherein the capacitive coupling circuitry is configured such that the single-phase clock signal provides substantial charge to the output voltage of the at least one capacitive charge pump. The capacitive energy transfer converter of claim 26 , wherein the capacitive coupling circuitry is configured such that the clock signal does not conduct substantial charge to the output voltage of the at least one capacitive charge pump.

The capacitive energy transfer converter of claim 26 , wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter. The capacitive energy transfer converter of claim 26 , wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit. A capacitive energy transfer converter for generating an output voltage supply within a circuit, including: a charge pump apparatus for generating an output voltage supply within a circuit, comprising: 1 a transfer capacitor;.

The capacitive energy transfer converter of claim 31 , wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter. The capacitive energy transfer converter of claim 31 , wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit. A clock generating circuit configured to be coupled to a capacitive charge pump for controlling alternate charging and discharging of an associated transfer capacitor of the capacitive charge pump during non-overlapping periods, the clock generating circuit including: a a current-starved ring oscillator configured to provide a single-phase clock signal to the capacitive charge pump; and.

The clock generating circuit of claim 34 , wherein the clock generating circuit is embodied within a monolithic integrated circuit. A clock generating circuit configured to be coupled to a capacitive charge pump for controlling alternate charging and discharging of an associated transfer capacitor of the capacitive charge pump during non-overlapping periods, the clock generating circuit configured to provide a single-phase substantially sine-like clock signal coupled capacitively to the capacitive charge pump, the clock signal generating circuit including: a voltage rate limiter circuitry to limit a rate of voltage change for the generated single-phase substantially sine-like clock signal; and.

The clock generating circuit of claim 36 , wherein the clock generating circuit is embodied within a monolithic integrated circuit. A clock generating circuit configured to be coupled to a capacitive charge pump for controlling alternate charging and discharging of an associated transfer capacitor of the capacitive charge pump during non-overlapping periods, the clock generating circuit configured to provide a substantially sine-like clock signal for capacitively coupling, without conveying substantial transfer current, to the capacitive charge pump.

The clock generating circuit of claim 38 , wherein the clock generating circuit is embodied within a monolithic integrated circuit. A clock generating circuit configured to be coupled to a capacitive charge pump for controlling alternate charging and discharging of an associated transfer capacitor of the capacitive charge pump during non-overlapping periods, the clock generating circuit configured to provide a clock signal to the capacitive charge pump, the clock generating circuit including active limiting circuitry for limiting a rate of voltage change of the clock signal during both positive transitions and negative voltage transitions such that the clock signal is substantially sine-like.

The clock generating circuit of claim 40 , wherein the clock generating circuit is embodied within a monolithic integrated circuit. USB2 en. EPB1 en. JPB2 en. WOA2 en. EPA2 en. Signal amplification circuit, optical receiver circuit, optical module, and data exchange system.

Buckwalter, B. Analui, and A. Buckwalter, M. Meghelli, D. Friedman, and A. Parker and K. Kratyuk, P. Hanumolu, U. Moon, and K. Mayaram, A design procedure for all-digital phaselocked loops based on a charge-pump phase-lockedloop analogy, IEEE Trans. Widrow and S. Stearns, Adaptive signal processing, Prentice Hall, [13] R. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. Balsara, 1. Now he is with GCT semiconductor. His research interests include low-power VLSI system, mixed-mode signal-processing IC design, all-digital clock and data recovery circuits, and RF circuits.

Suhwan Kim received the B. In , Dr.


  1. 1 сообщение в этой теме.
  2. - Class of 2002.
  3. O czym on myślał - PiotrexKoszlin;

His research interests encompass high-performance and low-power analog and mixed signal circuits and technology, digitally compensated analog and RF circuits, and driving methods and circuits for flat panel display. Deog-Kyoon Jeong received the B. Due to the relatively slower bus clocks. USB 3.

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